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Maxim-Integrated /max32520 /DMA /CH[7] /ST

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Interpret as ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)CH_ST 0 (inactive)IPEND 0 (CTZ_ST)CTZ_ST 0 (RLD_ST)RLD_ST 0 (BUS_ERR)BUS_ERR 0 (TO_ST)TO_ST

CH_ST=dis, IPEND=inactive

Description

DMA Channel Status Register.

Fields

CH_ST

Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).

0 (dis): Disable.

1 (en): Enable.
IPEND

Channel Interrupt.

0 (inactive): No interrupt is pending.

1 (pending): An interrupt is pending.
CTZ_ST

Count-to-Zero (CTZ) Event Interrupt Flag
RLD_ST

Reload Event Interrupt Flag.
BUS_ERR

Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
TO_ST

Time-Out Event Interrupt Flag.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk